Generally, semiconductor manufacturers such as semiconductor foundries (which accept manufacturing orders from many customers with different designs) perform new tape outs (NTOs) on a regular basis, as new designs and/or new process nodes (e.g., 90 nm, 65 nm, etc.) are introduced. In most of these NTOs for designs greater than 65 nm, a single process condition, such as the critical dimension of the active area can effectively control the manufacturing such that, when that single critical dimension is met within a certain sensitivity, the remaining process conditions will also meet the specifications required for the devices. Given such a simple, single-stage sensitivity of process nodes that are 65 nm or greater, engineers would be able to take a customer's specifications together with the single stage process conditions and manually map them to assign a recipe, or specific operating specifications, for the manufacturing of the desired design at the desired process node.
However, when the processes and designs are scaled down to nodes smaller than 65 nm, the single-stage sensitivity is not as effective. At such sizes, each of the process variables or stages interact with the other stages, such that no single stage may control the desired parameters as in the larger nodes. Instead, unintended consequences could occur if decisions are based on a single parameter instead of all of the parameters.
Additionally, having human operators and engineers making manual decisions about which process recipe to use also runs the risk of human error. Such errors can be time consuming and costly to analyze and correct and, as such, can lead to long cycle times while these errors are corrected. These long cycle times can slow down and delay the eventual manufacturing of the desired device.